W91031 Datasheet, PDF (24/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
Tip/Ring
1st Ring
Ch. seizure Mark
Message
A
B
C
D
E
F
INTN
(M-mode
or C-mode)
...
...
RNGON
2nd Ring
SLEEP
Note 1
Note 3 Note 4
FSKE
Note 2
DET
(C-mode)
FCDN
FDRN
...
...
DCLK
DATA
...101010...
Data
Note 5
Figure 9-3. Input and Output Timing of Bellcore On-hook Data Transmission
A = 2 sec typical
B = 250−500 mS
C = 250 mS
D = 150 mS
E = Depends on data length
MAX C + D + E = 2.9 to 3.7 sec
F ≥ 200 mS
Notes :
1. The CPE designer may choose to wake up the W91031 only after the end of the RNGON signal to conserve power for
a battery operated CPE. The delay from RNGON to SLEEP (and FSKE) is the reactive time of the microcontroller.
2. The CPE designer may choose to set FSKE to be always high while the CPE is on-hook, to ensure the FSK emodulator
does not react to other in-band noise.
3. The microcontroller places the W91031 in a sleep condition after FCDN has become inactive.
4. The W91031 may not be woken up at this ring signal after the FSK data has been processed.
5. If the W91031 has been woken up at the 2nd ring, the microcontroller times out if FCDN is not activated and then puts the
W91031 into a sleep condition.
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