W25X05CLUXIG-TR Datasheet, PDF (23/47 Pages) Winbond – 1M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

W25X10CL
8.1.19 Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with the “Fast Read Dual I/O” instruction to
provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus
allow true XIP (execute in place) to be performed on serial flash devices.
M7-0 need to be set by the Dual I/O Read instruction. M5-4 are used to control whether the 8-bit SPI
instruction code BBh is needed or not for the next command. When M5-4 = (1,0), the next command
will be treated same as the current Dual I/O Read command without needing the 8-bit instruction code;
when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can be
accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.
8.1.20 Continuous Read Mode Reset (FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in figure 13.
/CS
CLK
Mode 3
Mode 0
Mode Bit Reset
for Dual I/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
IO ₀
FFFFh
IO ₁
Don’t Care
Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O
Since W25X10CL does not have a hardware Reset pin, so if the controller resets while W25X10CL
are set to Continuous Mode Read, the W25X10CL will not recognize any initial standard SPI
instructions from the controller. To address this possibility, it is recommended to issue a Continuous
Read Mode Reset instruction as the first instruction after a system Reset. Doing so will release the
device from the Continuous Read Mode and allow Standard SPI instructions to be recognized.
To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh”.
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Publication Release Date: February 17, 2014
Revision G