W25X05CLUXIG-TR Datasheet, PDF (15/47 Pages) Winbond – 1M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

W25X10CL
8.1.10 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase
and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,
shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then
driving /CS high.
/CS
CLK
Mode 3
Mode 0
DI
(IO₀)
DO
(IO₁)
01234567
Instruction (06h)
Mode 3
Mode 0
High Impedance
Figure 4. Write Enable Instruction Sequence Diagram
8.1.11 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits.
This gives more flexibility to change the system configuration and memory protection schemes quickly
without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status
Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)
instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable
Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status
Register bit values.
Instruction (50h)
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
- 15 -
Publication Release Date: February 17, 2014
Revision G