W25X05CLUXIG-TR Datasheet, PDF (20/47 Pages) Winbond – 1M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

W25X10CL
8.1.17 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins, IO₀ and IO₁. This allows data to be transferred from the
W25X10CL at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal
for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO₀ pin should be high-impedance prior to the falling edge of the
first data out clock.
/CS
CLK
DI
(IO₀)
DO
(IO₁)
/CS
CLK
DI
(IO₀)
DO
(IO₁)
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (3Bh)
24-Bit Address
23 22 21
*
High Impedance
3210
* ^{= MSB}
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks
IO₀ switches from
Input to Output
0
64206420642064206
High Impedance
75317531753175317
* ^{Data Out 1}
* ^{Data Out 2}
* ^{Data Out 3}
* ^{Data Out 4}
Figure 11. Fast Read Dual Output Instruction Sequence Diagram
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Publication Release Date: February 17, 2014
Revision G