W19B160BT Datasheet, PDF (13/48 Pages) Winbond – 16Mbit, 2.7~3.6 volt CMOS flash memory

W19B160BT/B DATA SHEET
To return to read mode and exit the auto select mode, the system must write the reset command.
6.2.4 Byte/Word Program Command Sequence
The device can be programmed either by word or byte, which depending on the state of the #BYTE
pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by
writing two unlock write cycles, followed by the program setup command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The device automatically
provides internally generated program pulses and verifies the programmed cell margin.
Once the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please
note that a hardware reset will immediately stop the program operation. The program command
sequence should be reinitiated when the device has returned to the read mode, in order to ensure
data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that device to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can change “0” to “1.”
6.2.5 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7,
DQ6, or RY/#BY. Please refer to the Write Operation Status section for information on these status
bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when the device has returned to reading array data.
6.2.6 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase
command sequence, which is followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations is not required in system.
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Publication Release Date:Jan.04, 2008
Revision A5