TC94A29FB Datasheet, PDF (9/20 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC94A29FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
Power supply pins for the controller block.
8
MV_DD
Normally, V_DD = 3.0 to 3.6 V.
When only the CPU operates (when the
75-kHz/32.768-kHz oscillator is used), it can
operate at
V_DD = 1.8 to 3.6 V.
In the backup state (when the CKSTP
Power supply pins for
controller block
instruction is executed), current dissipation
decreases (10 mA or below), allowing the power
supply voltage to be reduced to 1.0 V.
Raising the voltage on MVDD pin from 0 V to
1.8 V or higher triggers a system reset, causing
the program to start from address 0 (power-on
reset).
9
MV_SS
(Note) At power-on reset operation, allow 1 ms
to 50 ms while the device power supply
voltage rises.
(Note) The backup current is the total of
currents for CV_DD, MV_DD and DV_DD.
Remarks
MV_DD
MV_SS
17
PDO
Output pin for a phase error signal between the
EFM and PLCK signals.
Drives one of four values: AV_DD, Hi-Z,
V_REF, AV_SS
AV_DD
R_out4
AV_SS
V_REF
TMAX detection result output pin.
Longer than specified cycle: Drives a high
18
TMAX
CD processor control
input/output pin
level (AV_DD)
Shorter than specified cycle: Drives a low
level (AV_SS)
Within specified cycle: Hi-Z
AV_DD
AV_SS
19
LPFN
20
LPFO
21
VCOF
22
AV_SS
Inverted input pin for PLL low-pass filter
amplifier.
Output pin for PLL low-pass filter amplifier.
VCO filter pin
Ground pin for analog block
V_REF
LPFN
LPFO
AV_DD
V_REF
VCOF
VCO
¾
9
2003-04-01