TC94A29FB Datasheet, PDF (6/20 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Pin
No.
Symbol
Pin Name
Function and Operation
TC94A29FAG/FB
Remarks
24-bit CMOS I/O port and 3-bit N-channel
open-drain I/O port.
LCD
voltage
52 P2-0/COM1
Input/output can be specified for each bit. When
the P6-0 to P6-3 pins are used as I/O port input,
MV_DD
each pin can be pulled up or down by program.
53
54
P2-1/COM2
P2-2/COM3
I/O port 2
/LCD common output
When the P5-1 (BRK3) to P7-2 (BRK16) pins
are used as I/O port input and backup release
for clock stop mode or wait mode is enabled for
those pins (enabled/disabled in port units), a
55 P2-3/COM4
change in any of the pins can release the
backup state. The P7-0 to P7-2 pins constitute
MV_DD
an N-channel open-drain I/O port, to which a
voltage of up to 5.5 V can be applied.
Input
instruction
I/O ports 2 to 6 can be set to LCD driver output
pins by program. The COM1 to COM4 pins
drive common signals to the LCD panel while
the S1 to S16 pins drive segment signals. The
COM1 to COM4 signals configure a matrix with
the S1 to S16 signals to display up to 64
LCD
voltage
segments.
MV_DD
When the LCDoff bit is set to 0, the COM1 to
COM4 and S1 to S4 pins are collectively set to
LCD output. For S5 to S16, the program can
specify either I/O port or segment output
56
TEST
/P3-0/S1
Test input
individually for each pin.
/I/O port 3-0
/LCD segment output
The LCD can be driven by the 1/4-duty, 1/2-bias
method (frame frequency: 62.5 Hz) or the
1/4-duty, 1/3-bias method (frame frequency: 125
MV_DD
Hz). When the 1/2 bias method is set, three
common output levels (MVDD, 1/2MVDD and
Input
instruction
GND) and two segment output levels (MVDD
and GND) appear on the pins. When the 1/3
R_IN2
bias method is set, four common and segment
Reset signal
output levels (MVDD, 1/3MVDD, 2/3MVDD and
GND) appear on the pins.
MV_SS
Upon a system reset or after clock stop mode is
57
P3-1/S2
released, a non-select waveform (bias voltage)
58
P3-2/S3
I/O port 3
is driven and the DISP OFF bit is set to 0, after
which the common signals are driven.
/LCD segment output
59
P3-3/S4
During a system reset ( RESET = low), the
TEST/P3-0/S1 pin is pulled down and accepts
test mode input. This pin should be left open or
applied low level during a reset.
60
P4-0/S5
The P5-1 to P6-3 and P1-0 to P1-2 pins can be
set to CD processor-dedicated pins on a per pin
61
P4-1/S6
I/O port 4
basis. The CD processor functions are as
62
P4-2/S7
/LCD segment output ^follows:
LCD
voltage
MV_DD
MV_DD
63
P4-3/S8
(Continued on next page)
Input
instruction
6
2003-04-01