TC94A29FB Datasheet, PDF (4/20 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Block Diagram
TC94A29FAG/FB
XI
XO
DV_DD
RO
DV_SS
LO
DVR
Clock gene.
Crystal
OSC
CD clock
ZDET
CV_DD
CV_SS
PWM
DA
V_REF
V_REF
V_REF
Data
slicer
RFI
SLCO
Servo
control
AD
V_REF
ROM
RAM
Digital equalizer
Automatic adjustment
circuit
CLV
servo
Sub code decoder
PLL
TMAX
TMAX
PDO
Synchronous
guarantee EFM
decoder
VCO
V_REF
V_REF
VCOF
LPFO
LPFN
Audio out
Digital out
CD Reset
16-k SRAM
Correction circuit
P8-0/MX1/OSC (BRK1)
P8-1/MXO (BRK2)
CR
OSC
Crystal
OSC
Port 8
SBSY
INTR
Timer
Interrupt
cont.
MPX
CPU clock
Microcontroller interface
Reset
SBSY
BCK, LRCK, AOUT, DOUT
IPF, SBOK, CLCK, DATA, SFSY
Data Reg (16 bits)
Mask ROM
(16 ´ 8192 Steps)
G-Reg.
RAM
(4 ´ 512 words)
Serial
interface
(SIO)
Program
Counter
Instruction
Decoder
P7-0/SCK2/RX2 (BRK14)
P7-1/SDIO2/TX2 (BRK15)
P7-2/INTR/SI2 (BRK16)
Port 7
Stack Reg.
(16 Levels)
Bias
BCK, LRCK, AOUT, DOUT, IPF, SBOK,
CLCK, DATA, SFSY, SBSY
LCD Driver/IO Port 2, 3, 4, 5, 6
R/W Buf.
ALU
F/F
Reset
Power on Reset
AD
conv.
20-bit
counter ^Buzzer
Port 1
SIO
RESET
MV_DD
MV_SS
4
2003-04-01