TC94A29FB Datasheet, PDF (11/20 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Pin
No.
Symbol
35
RFGC
36
TEBC
Pin Name
Function and Operation
Control signal output pin for adjusting RF
amplitude. Drives three-level PWM signal
(PWM carrier = 88.2 kHz).
Tracking balance control signal output pin.
Drives three-level PWM signal
(PWM carrier = 88.2 kHz).
TC94A29FAG/FB
Remarks
AV_DD
R_out3
V_REF
CD processor control ^{APC circuit ON/OFF signal output pin. When}
37
SEL
input/output pin
laser is turned on, this pin will be in a
high-impedance state.
AV_DD
38
FMO
Feed equalizer output pin. Drives three-level
PWM signal (PWM carrier = 88.2 kHz).
AV_DD
R_out3
39
DMO
Disc equalizer output pin. Drives three-level
PWM signal (PWM carrier = 88.2 kHz).
V_REF
40
CV_DD
Logic power supply pins for the CD processor
block and 16.9344-MHz dedicated crystal
Power supply pins
oscillator. Normally, the same power supply as
that for the MV_DD and MV_SS pins is connected.
In CD standby mode, current dissipation
decreases.
43
CV_SS
41
XO
Input/output pins for the CD
processor-dedicated crystal oscillator. Connect
a 16.9344-MHz crystal oscillator. This clock is
used as the CD processor system clock and
controller system clock. Upon a system reset,
this clock is supplied as the controller system
XO
clock and starts the CPU.
The crystal oscillator can be stopped by
Crystal oscillator pins program. If the 75/32.768-kHz or CR oscillator is
selected as the controller system clock, the CD
processor oscillator is stopped by program
XI
when the CD processor is turned off.
42
XI
(Note) When switching the controller system
clock from the controller oscillator to the
CD crystal oscillator, make sure that the
CD crystal oscillator is sufficiently
stable.
CV_DD
CV_SS
R_out1
R_fXT1
CV_DD
CV_SS
11
2003-04-01