TC94A29FB Datasheet, PDF (7/20 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC94A29FAG/FB
Pin
No.
Symbol
Pin Name
Function and Operation
Remarks
●BCK: Bit clock output pin. One of three
frequencies, 32, 48 or 64 can be
specified using a CD command.
At normal speed: 32 f_s = 1.4112 MHz
●LRCK: LR channel clock output pin. For the L
channel, this pin drives a low level. For
64
P5-0/S9
I/O port 5-0
/LCD segment output
the R channel, it drives a high level.
The polarity can be inverted using a
CD command.
LCD
voltage
MV_DD
At normal speed: 44.1 kHz
●AOUT: Audio data output pin. Either MSB first
or LSB first can be specified using a
Input
CD command.
instruction
MV_DD
●DOUT: Digital data output pin. It drives data at
up to double speed (complying with
CP-1201).
●IPF: Correction flag output pin. If the AOUT
P5-1/S10
1
/BCK
(BRK3)
output is C2 error detection/correction,
a high level appears to indicate an
uncorrectable symbol. (Also called
C2PO)
2
P5-2/S11
/LRCK
(BRK4)
I/O port 5
/LCD segment output
/CD processor
function
●SBOK: CRCC test result output pin for
subcode Q data. A high level appears
when the data has passed the test.
P5-3/S12
3
/AOUT
(BRK5)
●CLCK: Clock input/output pin for reading
subcode P to W data. The input/output
polarity can be inverted using a CD
Input
instruction
command.
Release
●DATA: Subcode P to W data output pin.
enable
LCD
voltage
MV_DD
MV_DD
●SFSY: Frame sync signal output pin for
playback.
●SBSY: Block sync signal output pin for
subcode. When a subcode sync is
AD input
P6-0/S13
4
/ADin1
/DOUT
(BRK6)
detected, a high level appears at S1.
The controller enables CD interrupts.
When an interrupt occurs on the falling
edge of the SBSY signal, the program
jumps to address 2.
LCD
voltage
MV_DD
P6-1/S14
5
/ADin2
(Note) Interrupts should not be enabled when
CD processor operation is undefined.
/IPF
I/O port 6
P6-0 to P6-3 pins have multiplexed functions for
(BRK7)
/LCD segment output ^{the on-chip 6-bit 4-channel AD converter analog}
P6-2/S15
6
/ADin3
/SBOK
(BRK8)
P6-3/S16
/CD processor
function
input. The on-chip AD converter uses
successive approximation. The conversion time
is 242 ms when the 16.9344-MHz crystal
oscillator is used and 7 instruction cycles
(280 ms) when the 75-kHz crystal oscillator is
used. The program can specify necessary pins
Input
instruction
Release
enable
R_IN1
MV_DD
7
/ADin4
for AD analog input on a per bit basis. The
/CLCK
internal power supply (MV_DD) is used as the
(BRK9)
reference voltage. When the P6-0 to P6-3 pins
are used as I/O port input, each pin can be
pulled up or down by program.
MV_DD
MV_SS
(Continued on next page)
7
2003-04-01