TC94A48FG Datasheet, PDF (8/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

[TMGA]
Bit
15-14
13
12-7
6
5-3
2-0
Default
＊
＊
＊
Contents
Reserved
Fixed to “0”
DSP clock output select
0 Disable
1 Enable
Reserved
Fixed to “0”
MCKO clock output select
0 1/1 Xi clock
1 1/2 Xi clock
Reserved
Fixed to “0”
DSP clock divider setting (1/J)
000 1/1
001 1/2
010 1/4
011 1/8
100 1/16
101 1/3
110 1/6
111 Prohibit
[TMGB]
Bit
15-14
13
12-8
7-0
Default
＊
＊
＊
＊
Contents
LRCKo/BCKo clock select
00 FS1/FS32(BCK=fs32)
01 FS1/FS64(BCK=fs64)
10 FS2/FS64(BCK=fs32)
11 FS2/FS128(BCK=fs64)
LRCKo/BCKo output clock select
0 Disable
1 Enable
Reference clock divider setting (1/M)
00h 1/1
01h 1/2
・
・
09h 1/10
・
1Fh 1/32
Variable clock divider setting (1/N)
00h 1/1
01h 1/2
・
・
3Fh 1/64
・
FFh 1/256
8
TC94A48FG
2005-09-28