TC94A48FG Datasheet, PDF (5/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

TC94A48FG
Description of Operation
1. Timing System
The TC94A48FG uses pulses from the XI-XO pins as the reference clock. The system is divided into blocks
that use the reference clock directly or by dividing its frequency and blocks that operate on a clock the PLL
generates based on the crystal resonation clock. The analog and microcontroller interface blocks operate on
the crystal resonation clock while the DSP block operates on the PLL-generated clock.
Crystal
Input=
256fs
PLL
Divider
Dividing
Clock for DSP
PLL-generated
Clock for Analog Block (256fs)
Clock for Analog Block (256fs or 512fs)
Timing output to pins
(LRCKO,BCKO,MCKO)
Crystal precision
Figure 1 Timing System
The system can divide the clock from the crystal and provide three types of clock from output pins.
Xi
Xo
ｆxi = 11.2896MHz
(44.1kHz×256)
MCKO Clock LRCKO, BCKO Clock
fs256
×1/2 ～ ×1/512
fs128～fs0.5
REFCK
×1/M
VARCK
Phase
Comp.
VCO
×1/Ｎ
PLL
×1/Ｊ
Figure 2 Block diagram of clock generator circuit
ADC, DAC
MAF, ΣΔ
Audio I/F
MCU I/F
DSP
5
2005-09-28