TC94A48FG Datasheet, PDF (20/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

TC94A48FG
2.2.2 Data Transfer Method in I²C Mode
(1) Program boot and program start
The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to
003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted
to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a
program loading process must follow the interrupt vector address. For a program boot, the 24-bit
command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to
"1" (command = xxxx60h).
The command must be followed by 16-bit program data, set in lower bits in 24-bit data.
The write address is automatically incremented (by one) from the command (000h). The program boot
completes once an end condition is transmitted upon transferring the required number of words. The
write address for a program boot always starts from the command (000h). To start the program,
transfer a 24-bit command with the soft reset bit cleared and then transmit an end condition without
transferring data.
Figure 14 shows the program boot and program start procedure.
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2005-09-28