TC94A48FG Datasheet, PDF (23/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

TC94A48FG
(3) Reading 24-bit data
When the host microcontroller reads data from the TC94A48FG during the execution of a program, it
sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of
words to be read. Then, it transfers the 24-bit command, waits about 1fs, and then transfers an I2C
address of 31h, followed by a start condition. Finally, it reads a required number of 24-bit data words.
During a read, the host microcontroller should set the ACK bits to low but the ACK bit accompanying
the last eight bits of data must be high, thus causing the TC94A48FG to relinquish the SDA bus line
so that the host microcontroller can transmit a stop condition.
The host microcontroller should wait about 1fs after transferring a command because it has to wait
until the data to be read is set in the data buffer of the TC94A48FG.
Figure 16 shows the 24-bit data read procedure.
ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ
Transfer I2C Ａｄｄｒｅｓｓ(30h)
If ACK = “H” , restart from
START condition.
Check ACK bit = “L”
Transfer 24-bit command
(data read = xxxx1xh)
Set a 16-bit address and the number
of words to be transferred.
Wait about 1fs
ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ
Transfer I2C Ａｄｄｒｅｓｓ(31h)
Check ACK bit = “L”
Read 24-bit data (1)
Read 24-bit data (2)
If ACK = “H” , restart from
START condition.
Can read up to eight 24-bit
data words
Read 24-bit data (n)
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Set the last ACK bit to “H”
Data read finished
Figure 16 shows the 24-bit Data Read Procedure
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2005-09-28