TC94A48FG Datasheet, PDF (6/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

1.1 Timing register setting
[AIFA]
Bit
15-14
13-12
11
10
9
8
7-6
5-4
3-2
1-0
Default
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
Contents
BCKi-1 clock frequency
00 32fs
01 48fs
10 64fs
11 64fs
BCKi-0 clock frequency
00 32fs
01 48fs
10 64fs
11 64fs
LRCKi-1 polarity
0 Lch=Low (interrupt by fall edge)
1 Lch=High (interrupt by rise edge)
LRCKi-0 polarity
0 Lch=Low (interrupt by fall edge)
1 Lch=High (interrupt by rise edge)
SDi clock select
0 LRCKi-0/BCKi-0
1 LRCKi-1/BCKi-1
SDo clock select
0 LRCKi-0/BCKi-0
1 LRCKi-1/BCKi-1
SDi input format
00 LSB justified
01 MSB justified
10 _I²_S
11 _I²_S
SDi input bit clock
00 16bit
01 18bit
10 20bit
11 24bit
SDo output format
00 LSB justified
01 MSB justified
10 _I²_S
11 _I²_S
SDo output bit clock
00 16bit
01 18bit
10 20bit
11 24bit
TC94A48FG
Note 2: In 48fs frequency setup of BCKi-1 and BCKi-0, LRCKi/BCKi coresponds only an input, and LRCKo / BCKo
does not correspond.
6
2005-09-28