TC94A48FG Datasheet, PDF (12/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

TC94A48FG
The audio input block and output block support different clock settings. Input and output port
settings are, however, shared as follows:
LR Clock Setting for Input Block
Mode
Master Mode
Slave Mode
Signal
Signal delivered to LRCKO pin (crystal resonation clock divided)
LRCKI0 pin input
LRCKI1 pin input
Bit Clock Setting for Input Block
Mode
Master Mode
Slave Mode
Signal
Signal delivered to BCKO pin (crystal resonation clock divided)
BCKI0 pin input
BCKI1 pin input
LR Clock Setting for Output Block
Mode
Master Mode
Slave Mode
Signal
Signal delivered to LRCKO pin (crystal resonation clock divided)
LRCKI0 pin input
LRCKI1 pin input
Bit Clock Setting for Input Block
Mode
Master Mode
Slave Mode
Signal
Signal delivered to BCKO pin (crystal resonation clock divided)
BCKI0 pin input
BCKI1 pin input
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2005-09-28