TC94A48FG Datasheet, PDF (24/36 Pages) Toshiba Semiconductor – Single-chip Audio Digital Signal Processor

TC94A48FG
(4) Triggering and terminating a soft reset
A soft reset is required before the system can start a program after program boot or restart a
program.
A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit
cleared terminates a soft reset.
When trigging or terminating a soft reset, transmit a stop condition after transferring the 24-bit
command because no data needs to follow the command.
Figure 17 shows the procedure for triggering or terminating a soft reset.
ＳＴＡＲＴ　Ｃｏｎｄｉｔｉｏｎ
Transfer I2C　Ａｄｄｒｅｓｓ（３０ｈ）
Check ACK bit = “L”
Transfer 24-bit command
(soft reset ON/OFF = 0000x0h)
ＳＴＯＰ　Ｃｏｎｄｉｔｉｏｎ
If ACK = “H” , restart from
START Condition.
If a system crash(malfunction)
occurs, perform a hard reset
prior to a soft reset.
“1” triggers a reset
“0” terminates a reset
Soft reset triggered or terminated
Figure 17 Procedure for Triggering or Terminating a Soft Reset
3. Write and Read Commands
The specifications of write and read commands depend on the built-in program. For details, refer to the
program explanation data sheet.
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2005-09-28