TMPR3927 Datasheet, PDF (476/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Appendix A TX3927 Programming Samples
lw
t0,REG_SIZE*8(sp)
lw
lw
sync
jr
rfe
nop
v0,REG_SIZE*2(sp)
sp,REG_SIZE*26(sp)
k1
/* Flush the write buffer to memory. */
/* Return to the user program. */
99:
b
nop
/* stack overflow */
99b
Interrupt handling flow:
(1) Examine the ExCode field of the Cause register and pass control to the appropriate exception
handler (swIntVect[0-12]). (In this example, only the external interrupt (ExCode = 0) handling
routine is provided.)
(2) For an external interrupt (swIntVect[0]), read the IP field of the Cause register and pass control to
the appropriate handler (swIntVect[13-30]).
This routine sets the interrupt stack, and saves and restores registers. It does not save all registers
because the program assumes that the body of interrupt handling is written in C. Those registers
not saved here will be saved and restored, as required, in the C function.
When this example is used, the actual interrupt handling section is written in C, as follows:
int C_int_timer0(void)
{
static int count = 0;
count++;
/* Count number of interrupts */
CPUReg->TREG[0].TMTISR = 0; /* Negate interrupt */
return 0;
}
The C function should include the following processes:
• Appropriately handles the interrupt.
• Clears the interrupt condition.
• (Optionally) allows nested interrupts.
A-26