TMPR3927 Datasheet, PDF (102/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 8 SDRAM Controller
Table 8.5.4 Address Mapping for 32-bit SDRAM (2/2)
Row address width = 12
Column address width = 11
Address bit
5
6
7
8
9 10 11 12 13 14 15 16
ADDR [19 : 5]
(AP)
Column
address
2
3
4
5
6
7
8
9 22 23 L/H 24
Row address
10 11 12 13 14 15 16 17 18 19 20 21
17 18 19
(B1) (B0)
25 26 25
25 26 25
Row address width = 13
Column address width = 8
Address bit
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
ADDR [19 : 5]
(AP)
(B1) (B0)
Column
address
2
3
4
5
6
7
8
9 23 24 L/H 21 22 24 23
Row address
10 11 12 13 14 15 16 17 18 19 20 21 22 24 23
Row address width = 13
Column address width = 9
Address bit
ADDR [19 : 5]
Column
address
Row address
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
(AP)
(B1) (B0)
2
3
4
5
6
7
8
9 23 24 L/H 21 22 25 24
10 11 12 13 14 15 16 17 18 19 20 21 22 25 24
Row address width = 13
Column address width = 10
Address bit
ADDR [19 : 5]
Column
address
Row address
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
(AP)
(B1) (B0)
2
3
4
5
6
7
8
9 23 24 L/H 21 22 26 25
10 11 12 13 14 15 16 17 18 19 20 21 22 26 25
Row address width = 13
Column address width = 11
Address bit
ADDR [19 : 5]
Column
address
Row address
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
(AP)
(B1) (B0)
2
3
4
5
6
7
8
9 23 24 L/H 25 22 27 26
10 11 12 13 14 15 16 17 18 19 20 21 22 27 26
8-18