TMPR3927 Datasheet, PDF (442/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 19 Known Problems and Limitations
[Situations in Which This Problem Occurs]
This problem occurs as follows:
<PCIC Settings>
(1) The "never time-out" feature is enabled.
This is the case where bit 18 in the TC register is set to one. The reset value is zero.
(2) The TBL_OFIFO field (bits 7 to 4) in the TBL register is 01XX or 1X1X.
<Problem Occurrence Sequence>
This problem occurs when an external PCI bus master deasserts IRDY* to insert a wait state while it is
reading the last beat of a 16-Dword burst from the TX3927. The problem occurs as follows:
(1) When 15 Dwords have been read, the TX3927 falsely considers that the PCI transaction will complete
in the next clock cycle and terminates.
(2) The external PCI bus master deasserts IRDY* and keeps waiting for the next data item.
If the "never time-out" feature is enabled, the TX3927 can not terminate the transaction by asserting the
STOP* signal. Because the burst length of 16 Dwords is the same size as the OFIFO, the last one Dword will
remain in the OFIFO. As a result, the TX3927 can not read the next Dword into the OFIFO and thus can not
meet the trigger level at which a PCI bus cycle occurs.
Since the PCI transaction is not completed, the PCI bus master will not release the bus, causing it to be
locked.
[Workarounds]
There are two workarounds for this problem:
(1) Disable the "never time-out" feature.
That is, clear bit 18 of the TC register to zero. (The reset value is zero).
(2) Set the TBL_OFIFO field (bits 7 to 4) in the TBL register to a value other than 01XX or 1X1X.
[Operating System Usage Considerations]
See the section "Operating System Usage Considerations for ERT-TX3927-011 to ERT-TX3927-014" in
Section 19.15.
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