TMPR3927 Datasheet, PDF (183/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 10 DMA Controller
Bits
19
18:17
16
15:13
12
11
10
9
8
Mnemonic
CHDN
DNCTL
EXTRQ
INTRQD
INTENE
INTENC
INTENT
CHNEN
XTACT
Field Name
Description
Chain Done
Done Control
External Request
Internal Request
Delay
Interrupt Enable
on Error
Interrupt Enable
on Chain Done
Interrupt Enable
on Transfer Done
Chain Enable
Transfer Active
Chain Done (initial value: 0)
1: DMADONE* controls chained transfers instead of one DMA process. As an
output, DMADONE* will be asserted when DMA data chaining completes. As an
input, assertion of DMADONE* will cause the active channel to stop the chaining.
0: DMADONE* controls one DMA process instead of chained transfers. As an
outputs DMADONE* will be asserted upon completion of a DMA process. As an
input, assertion of DMADONE* will cause the channel to stop the entire DMA
transaction (the current transfer and the entire chaining operation).
Done Control (initial value: 00)
Enables or disables the validity of the DMADONE* signal.
00: DMADONE* is used neither as an output nor as an input.
01: DMADONE* is not used as an output. As an input, DMADONE* will cause the
current DMA process or chaining operation to terminate.
10: As an output, DMADONE* is asserted upon completion of a DMA process or
chaining operation. DMADONE* is not used (i.e., ignored) as an input.
11: When the channel is active, DMADONE* is used as an open-drain output. It is
asserted upon completion of a DMA process or chaining operation. As an input,
DMADONE* will cause the current DMA process or chaining operation to
terminate.
Note: Care must be taken when using open-drain mode because an external pull-up
resistor will cause the transition time of the output driver to increase.
External Request (initial value: 0)
Selects the transfer request mode.
1: Assertion of the external DMA request signal requests DMA service.
0: Internally generated request transfers. This mode is used for memory-to-memory
transfers.
Internal Request Delay (initial value: 000)
Limits the amount of bus utilization by setting an interval between two internally
generated transfer requests.
000: Minimum interval (Even in this case, the bus is once released and then
reacquired.)
001: 16 clock cycles
010: 32 clock cycles
011: 64 clock cycles
100: 128 clock cycles
101: 256 clock cycles
110: 512 clock cycles
111: 1024 clock cycles
Interrupt Enable on Error (initial value: 0)
1: Enables DMA interrupts for errors.
0: Disable DMA interrupts for errors.
Interrupt Enable on Chain Done (initial value: 0)
1: Enables DMA interrupts for chaining.
0: Disables DMA interrupts for chaining.
Interrupt Enable on Transfer Done (initial value: 0)
1: Enables DMA interrupts for end-of-transfer.
0: Disables DMA interrupts for end-of-transfer.
Chain Enable (initial value: 0)
Enables DMA data chaining.
1: Immediately upon completion of the transfers, the channel’s registers are
reloaded from the address specified in the Chained Address Register. Transfers
then continue uninterrupted.
0: The channel does not chain.
Transfer a Active (initial value: 0)
1: Starts DMA transfer on the channel. Prior to executing a DMA transfer, set
appropriate parameters in the register and then write a 1 to this bit. Writing a 0 to
this bit causes the transfer to halt gracefully; then resetting it to 1 restarts the
transfer. This bit is automatically cleared when the transfer completes normally or
halts due to an error.
Figure 10.3.2 Channel Control Registers (2/3)
10-7