TMPR3927 Datasheet, PDF (419/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 19 Known Problems and Limitations
19. Known Problems and Limitations
19.1 Programming Restrictions for the TMPR3927A
Since the TX39 processor core has caches and a write buffer, bus operations may be executed in a
different order from the order in which they are specified in a program. For example, writes to the registers
of the SDRAMC, ROMC and IRC modules may occur out of order.
(1) Routines residing in uncacheable and cacheable spaces
Programs that reside in uncacheable space (see Section 4.1, "Memory Mapping") execute instructions
and bus operations in the exact order in which they are specified. On the other hand, programs that
reside in cacheable space may execute instructions and bus operations out of order on cache hits. (Read
operations are given precedence.)
(2) sync instruction
The sync instruction stalls the instruction pipeline until any bus operations initiated prior to this
instruction are completed. The sync instruction delays the processor writes to the write buffer, but the
write buffer continues to drain, writing to peripheral registers.
(3) Write buffer
There are two cases where the write buffer gives precedence to a write operation over a read operation:
• When the processor core issues a read request to the target address of one of the write buffer
entries
• When the processor core issues an unchacheable read reference while the write buffer has
uncacheable write data
For example, compare the codes shown in Figure 19.1.1 and Figure 19.1.2, which are both intended to
set an interrupt mask level and then enable interrupts.
sw
mfc0
or
mtc0
r8, IRC_IRIMR_ADDR
r9, r12
r9, r9, r10
r9, r12
# Sets interrupt mask level in IRIMR.
# Reads CP0 Status register.
# Prepares data to be written to IP[4:0] and IEc. r10 = 0x00007c01
# Enables interrupts.
Figure 19.1.1 Program That Accepts Unintended Interrupt Requests
sw r8, IRC_IRIMR_ADDR
lw
r8, IRC_IRSSR_ADDR
mfc0
or
mtc0
r9, r12
r9, r9, r10
r9, r12
# Sets interrupt mask level in IRIMR.
# Previous write to IRIMR in uncacheable space occurs prior to
# this uncacheable read.
# Reads CP0 Status register.
# Prepares data to be written to IP[4:0] and IEc. r10 = 0x00007c01
# Enables interrupts.
Figure 19.1.2 Program That Masks Interrupt Requests As Intended
If the program shown in Figure 19.1.1 resides in cacheble space with the cache enabled, interrupts could
be enabled before a write to the IRIMR takes place. If that happens, the TMPR3927 could accept unintended
interrupt requests.
Notice that the program shown in Figure 19.1.2 includes an lw instruction to read the IRSSR, which is in
uncachaeble space. This causes the immediately preceding write to the IRIMR to take place first. Thus,
interrupts are always enabled after the IRIMR is written with a new mask level.
19-1