TMPR3927 Datasheet, PDF (332/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 12 PCI Controller (PCIC)
12.4.2 Configuration Cycles
To perform a PCI configuration transaction as an initiator in PIO mode, the Initiator Configuration
Address register (ICAR) must programmed. Then, a read or write to the Initiator Configuration Data
register (ICDR) causes the PCIC to translate the access into a PCI configuration cycle. The TX3927
performs type 0 configuration accesses.
During configuration accesses, the device with ID_SEL set to High will respond. If the TX3927
never functions as a target during PCI configuration cycles, ID_SEL must be tied Low.
12.4.3 Address Translation
The PCIC allows remapping of PCI transactions to the G-Bus space and G-Bus transactions to the
PCI space.
• When the PCIC is the initiator running in direct mode (G-Bus to PCI bus address translation)
When the TX39/H2 core accesses memory on the PCI bus, the PCIC compares the G-Bus
address from the TX39/H2 core with the contents of the ILBMMAR register. The MMAS register
holds a comparison mask that sets the variable memory region size. If there is an address match,
the PCI bus address is generated by replacing the high-order bits of the G-Bus address with the
corresponding bits of the IPBMMAR register. The remaining low-order bits of the G-Bus address
are passed unchanged. When the target is an I/O device, the registers shown in parentheses in
Figure 12.4.1 are used in address translation.
31
0
G-Bus address
Compare
31
0
ILBMMAR
(ILBIOMAR)
31
0
MMAS
(IOMAS)
1
1
1
1…1
1
1
0
0
0
0
0
0 ………… 0
0
0
0
0
0
0
0
31
0
IPBMMAR
(IPBIOMAR)
31
0
PCI bus address
Figure 12.4.1 Address Translation in Direct Initiator Mode (G-Bus to PCI bus address translation)
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