TMPR3927 Datasheet, PDF (199/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 10 DMA Controller
10.4.8 Timing for an External DMA Request (DMAREQ)
When the off-chip peripheral requires DMA service, it asserts the external DMA request signal
(DMAREQ) for a channel. The DMAREQ signal is internally cycled based on GBUSCLK (which runs
at half CPU operating frequency).
External DMA request pins can be configured for either edge or level sensitivity. If programmed as
edge-triggered, once the DMAC channel starts a DMA transfer, the next DMA request can be
recognized (i.e., one clock cycle before DMAACK is asserted). If programmed as level-sensitive, the
DMA channel recognizes the next DMA request two clock cycles before DMAACK is asserted. (Refer
to "10.5 Timing Diagrams.")
The request on the level-sensitive DMAREQ pin must remain asserted until the DMA transfer starts.
10.4.9 Configuration Errors
A configuration error results when a DMA channel is activated by bit 8 (Transfer Active) of the
Channel Control Register (CCRn) in the following circumstances:
(1) The two least-significant bits of the Chained Address Register (CHARn) are non-zero.
(2) The XFSZ field of the CCRn register specifies a transfer size of 8 bits (000) in single-address
mode.
(3) The XFSZ field of the CCRn register specifies a transfer size of 16 or 32 words (11x) in dual-
address mode.
(4) The XFSZ field of the CCRn register contains a reserved value (011).
(5) Either of the following conditions is detected when byte order reversing is enabled by bit 23 of the
CCRn register:
1) Single-address mode is selected.
2) Dual-address mode is selected, with the XFSZ field of the CCRn register programmed for a
transfer size of 8 or 16 bits (00x).
(6) Any of the following conditions is detected when the transfer size is 16 bits:
1) The least-significant bit of the Source Address Register (SARn) is 1.
2) The least-significant bit of the Source Address Increment Register (SAIn) is 1.
3) The least-significant bit of the Destination Address Register (DARn) is 1 in dual-address mode.
4) The least-significant bit of the Destination Address Increment Register (DAIn) is 1 in dual-
address mode.
(7) The least-significant bit of the Count Register (CNTRn) is 1 when the transfer size is 16 bits.
(8) Any of the following conditions is detected when the transfer size is 32 bits:
1) The two least-significant bits of the Source Address Register (SARn) are non-zero.
2) The two least-significant bits of the Source Address Increment Register (SAIn) are non-zero.
3) The two least-significant bits of the Destination Address Register (DARn) are non-zero in dual-
address mode.
4) The two least-significant bits of the Destination Address Increment Register (DAIn) non-zero in
dual-address mode.
(9) The two least-significant bits of the Count Register (CNTRn) non-zero when the transfer size is 32
bits.
10-23