TMPR3927 Datasheet, PDF (187/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

10.3.5 Source Address Registers (SARn)
Chapter 10 DMA Controller
0xFFFE_B004 (ch. 0),
0xFFFE_B024 (ch. 1),
0xFFFE_B044 (ch. 2),
0xFFFE_B064 (ch. 3)
31
16
SADDR
R/W
: Type

: Initial value
15
0
SADDR
R/W
: Type

: Initial value
Bits
31:0
Mnemonic
SADDR
Field Name
Source Address
Description
Source Address (initial value: undefined)
The Source Address Register is loaded with the physical address of the source for
dual-address transfers. For single-address transfers, this register is loaded with the
memory address, whether the transfer is from memory to I/O or from I/O to memory.
The address must be aligned, depending on the transfer size. For example, if the
transfer size is a 32-bit word, the low-order two bits of the address must be 0.
Figure 10.3.4 Source Address Registers
10-11