TMPR3927 Datasheet, PDF (429/512 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

Chapter 19 Known Problems and Limitations
[Workarounds]
There are two wrokarounds for this problem.
(1) Perform a PCI configuration read in Indirect mode. More specifically, program the following registers:
• Initiator Indirect Address Register (IPCIADDR) at address 0xFFFE_D150
• Initiator Indirect Data Register (IPCIDATA) at address 0xFFFE_D154
• Initiator Direct Command/Byte Enable Register (IPCIICBE) at address 0xFFFE_D0158
• Initiator Status Register (ISTAT) at address 0xFFFE_D044
In Direct mode, a PCI configuration read cycle is begun by the CPU reading the ICDR register. The
CPU read cycle does not end until the PCI configuration read cycle is completed.
In Indirect mode, a PCI bus cycle begins asynchronously from a CPU read access when the CPU writes
an address and command to the IPCIADDR and IPCIICBE registers respectively.
The result of a PCI configuration read is stored in the IPCIDATA register. The completion of a PCI bus
cycle can be determined by polling the ISTAT register. (Alternatively, an interrupt can be generated by
programming the Initiator Interrupt Mask (IIM) register at address 0xFFFE_D048.)
In Indirect mode, the CPU bus cycle completes without waiting for a response from a target PCI device.
Thus, no bus error will occur due to time-out.
It must be noted that, in Indirect mode, the value of the IPCIADDR register is placed onto PCIAD[31:0]
during the address phase of a PCI bus cycle and that the values of the ICMD and IBE fields in the
IPCICBE register are placed onto C_BE[3:0] as a PCI command and byte enables respectively.
See the "Programming Example" section for a sample program for Indirect mode. The correct operation
of the sample program is not guaranteed; it is the user's responsibility to verify its operation on a target
system.
(2) Disable bus time-out errors by clearing the TOE bit in the CCFG register.
Clearing the TOE bit disables all types of bus errors. However, since the bus master on the G-Bus keeps
waiting for an acknowledge from the target PCI device, there is still a chance of bus deadlock. For
example, the target PCI device might keep issuing retries without returning an acknowledge, causing the
CPU bus cycle to be deadlocked.
To prevent bus deadlocks, a watchdog timer should be used to detect a bus time-out and reset the whole
system on a time-out.
19-11