TMS320DM8127 Datasheet, PDF (98/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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Table 4-19. McASP1 Terminal Functions
SIGNAL
TYPE⁽¹⁾ OTHER ^{(2) (3)}
NAME
NO.
MUXED
DESCRIPTION
McASP1
MCA[1]_ACLKR/
MCA[1]_AXR[4]
M1
I/O
IPD
DVDD
MCA[1]
PINCNTL33
DSIS: 0
McASP1 Receive Bit Clock I/O
MCA[1]_AFSR/
MCA[1]_AXR[5]
M2
I/O
IPD
DVDD
MCA[1]
PINCNTL34
DSIS: 0
McASP1 Receive Frame Sync I/O
MCA[1]_ACLKX
U5
I/O
IPD
DVDD
–
PINCNTL31
McASP1 Transmit Bit Clock I/O
AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/
MCA[4]_AHCLKX/ R5
I/O
EDMA_EVT3/
TIM2_IO/
GP0[8]
IPD
DVDD
AUD_CLKIN1,
MCA[0], MCA[4],
EDMA, TIMER2,
GP0
PINCNTL15
DSIS: PIN
McASP1 Transmit High-Frequency Master Clock I/O
MCA[1]_AFSX
V3
I/O
IPD
DVDD
–
PINCNTL32
McASP1 Transmit Frame Sync I/O
MCA[3]_AXR[3]/
MCA[1]_AXR[9]/
J6
I/O
IPD
DVDD
MCA[3]
PINCNTL50
DSIS: PIN
MM: MUX1
MCA[0]_AXR[5]/
MCA[1]_AXR[9]
M3
I/O
IPD
DVDD
MCA[0]
PINCNTL26
DSIS: PIN
MM: MUX0
MCA[3]_AXR[2]/
MCA[1]_AXR[8]/
F2
I/O
GP0[20]
IPD
DVDD
MCA[3], GP0
PINCNTL49
DSIS: PIN
MM: MUX1
MCA[0]_AXR[4]/
MCA[1]_AXR[8]
R6
I/O
IPD
DVDD
MCA[0]
PINCNTL25
DSIS: PIN
MM: MUX0
MCA[2]_AXR[3]/
MCA[1]_AXR[7]/
TIM3_IO/
H2
I/O
GP0[15]
IPD
DVDD
MCA[2], TIMER3,
GP0
PINCNTL44
DSIS: PIN
McASP1 Transmit/Receive Data I/Os
MCA[2]_AXR[2]/
MCA[1]_AXR[6]/
TIM2_IO/
V5
I/O
GP0[14]
IPD
DVDD
MCA[2], TIMER2,
GP0
PINCNTL43
DSIS: PIN
MCA[1]_AFSR/
MCA[1]_AXR[5]
M2
I/O
IPD
DVDD
MCA[1]
PINCNTL34
DSIS: PIN
MCA[1]_ACLKR/
MCA[1]_AXR[4]
M1
I/O
IPD
DVDD
MCA[1]
PINCNTL33
DSIS: PIN
MCA[1]_AXR[3]/
MCB_CLKR
N6
I/O
IPD
DVDD
MCB
PINCNTL38
DSIS: PIN
MCA[1]_AXR[2]/
MCB_FSR
R3
I/O
IPD
DVDD
MCB
PINCNTL37
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 5.5.1, Pullup/Pulldown Resistors and Section 8.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
98
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