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| TMS320DM8127 Datasheet, PDF (241/365 Pages) Texas Instruments – DaVinci Video Processors | |||
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TMS320DM8127
SPRS712C â JUNE 2012 â REVISED MARCH 2014
9.6.3 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The MDIO module implements the 802.3 serial management interface to interrogate and control Ethernet
PHYs using a shared two-wire bus. Host software uses the MDIO module to configure the auto-
negotiation parameters of each PHY attached to the EMAC SW, retrieve the negotiation results, and
configure required parameters in the EMAC SW module for correct operation. The module is designed to
allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor. A single MDIO interface is pinned out to control the PHY configuration and status monitoring.
Multiple external PHYs can be controlled by the MDIO interface.
For more detailed information on the MDIO peripheral, see the 3PSW Ethernet Subsystem chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
9.6.3.1 MDIO Peripheral Register Descriptions
HEX ADDRESS
0x4A10 0800
0x4A10 0804
0x4A10 0808
0x4A10 080C
0x4A10 0810
0x4A10 0814
0x4A10 0818 - 0x4A10 081C
0x4A10 0820
0x4A10 0824
0x4A10 0828
0x4A10 082C
0x4A10 0830 - 0x4A10 087C
0x4A10 0880
0x4A10 0884
0x4A10 0888
0x4A10 088C
0x4A10 0990 - 0x4A10 08FF
Table 9-27. MDIO Registers
ACRONYM
VERSION
CONTROL
ALIVE
LINK
LINKINTRAW
LINKINTMASKED
-
USERINTRAW
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
-
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
-
REGISTER NAME
MDIO Version
MDIO Control
PHY Alive Status
PHY Link Status
MDIO Link Status Change Interrupt (Unmasked)
MDIO Link Status Change Interrupt (Masked)
Reserved
MDIO User Command Complete Interrupt (Unmasked)
MDIO User Command Complete Interrupt (Masked)
MDIO User Command Complete Interrupt Mask Set
MDIO User Command Complete Interrupt Mask Clear
Reserved
MDIO User Access 0
MDIO User PHY Select 0
MDIO User Access 1
MDIO User PHY Select 1
Reserved
9.6.3.2 MDIO Electrical Data/Timing
(see Figure 9-18)
NO.
1 tc(MDCLK)
tw(MDCLK)
4 tsu(MDIO-MDCLKH)
5 th(MDCLKH-MDIO)
Table 9-28. Timing Requirements for MDIO Input
Cycle time, MDCLK
Pulse duration, MDCLK high or low
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
OPP100/122/166
MIN
MAX
400
180
20
0
UNIT
ns
ns
ns
ns
Copyright © 2012â2014, Texas Instruments Incorporated
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Peripheral Information and Timings 241
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