TMS320DM8127 Datasheet, PDF (230/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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Table 9-14. Ethernet MAC Switch Registers (continued)
ARM/L3 MASTERS
EMAC HEX
ADDRESS RANGE
0x4A10 0148
0x4A10 014C
0x4A10 0150 – 0x4A10 017C
0x4A10 0180
0x4A10 0184
0x4A10 0188
0x4A10 018C
0x4A10 0190
0x4A10 0194
0x4A10 0198 – 0x4A10 019C
0x4A10 01A0
0x4A10 01A4
0x4A10 01A8
0x4A10 01AC
0x4A10 01B0
0x4A10 01B4
0x4A10 01B8
0x4A10 01BC
0x4A10 01C0
0x4A10 01C4
0x4A10 01C8
0x4A10 01CC
0x4A10 01D0
0x4A10 01D4
0x4A10 01D8
0x4A10 01DC
0x4A10 01E0
0x4A10 01E4
0x4A10 01E8
0x4A10 01EC
0x4A10 01F0
0x4A10 01F4
0x4A10 01F8
0x4A10 01FC
0x4A10 0200
0x4A10 0204
0x4A10 0208
0x4A10 020C
0x4A10 0210
0x4A10 0214
0x4A10 0218
0x4A10 021C
0x4A10 0220
0x4A10 0224
0x4A10 0228
ACRONYM
REGISTER NAME
TX_PRI6_RATE
TX_PRI7_RATE
–
TX_INTSTAT_RAW
TX_INTSTAT_MASKED
TX_INTMASK_SET
TX_INTMASK_CLEAR
CPDMA_IN_VECTOR
CPDMA_EOI_VECTOR
–
RX_INTSTAT_RAW
RX_INTSTAT_MASKED
RX_INTMASK_SET
RX_INTMASK_CLEAR
DMA_INTSTAT_RAW
DMA_INTSTAT_MASKED
DMA_INTMASK_SET
DMA_INTMASK_CLEAR
RX0_PENDTHRESH
RX1_PENDTHRESH
RX2_PENDTHRESH
RX3_PENDTHRESH
RX4_PENDTHRESH
RX5_PENDTHRESH
RX6_PENDTHRESH
RX7_PENDTHRESH
RX0_FREEBUFFER
RX1_FREEBUFFER
RX2_FREEBUFFER
RX3_FREEBUFFER
RX4_FREEBUFFER
RX5_FREEBUFFER
RX6_FREEBUFFER
RX7_FREEBUFFER
TX0_HDP
TX1_HDP
TX2_HDP
TX3_HDP
TX4_HDP
TX5_HDP
TX6_HDP
TX7_HDP
RX0_HDP
RX1_HDP
RX2_HDP
CPDMA_REGS Transmit (Ingress) Priority 6 Rate
CPDMA_REGS Transmit (Ingress) Priority 7 Rate
Reserved
CPDMA_INT TX Interrupt Status Register (Raw Value)
CPDMA_INT TX Interrupt Status Register (Masked Value)
CPDMA_INT TX Interrupt Mask Set Register
CPDMA_INT TX Interrupt Mask Clear Register
CPDMA_INT Input Vector (Read Only)
CPDMA_INT End Of Interrupt Vector
Reserved
CPDMA_INT RX Interrupt Status Register (Raw Value)
CPDMA_INT RX Interrupt Status Register (Masked Value)
CPDMA_INT RX Interrupt Mask Set Register
CPDMA_INT RX Interrupt Mask Clear Register
CPDMA_INT DMA Interrupt Status Register (Raw Value)
CPDMA_INT DMA Interrupt Status Register (Masked Value)
CPDMA_INT DMA Interrupt Mask Set Register
CPDMA_INT DMA Interrupt Mask Clear Register
CPDMA_INT Receive Threshold Pending Register Channel 0
CPDMA_INT Receive Threshold Pending Register Channel 1
CPDMA_INT Receive Threshold Pending Register Channel 2
CPDMA_INT Receive Threshold Pending Register Channel 3
CPDMA_INT Receive Threshold Pending Register Channel 4
CPDMA_INT Receive Threshold Pending Register Channel 5
CPDMA_INT Receive Threshold Pending Register Channel 6
CPDMA_INT Receive Threshold Pending Register Channel 7
CPDMA_INT Receive Free Buffer Register Channel 0
CPDMA_INT Receive Free Buffer Register Channel 1
CPDMA_INT Receive Free Buffer Register Channel 2
CPDMA_INT Receive Free Buffer Register Channel 3
CPDMA_INT Receive Free Buffer Register Channel 4
CPDMA_INT Receive Free Buffer Register Channel 5
CPDMA_INT Receive Free Buffer Register Channel 6
CPDMA_INT Receive Free Buffer Register Channel 7
CPDMA_STATERAM TX Channel 0 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 1 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 2 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 3 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 4 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 5 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 6 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM TX Channel 7 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM RX 0 Channel 0 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM RX 1 Channel 1 Head Desc Pointer ⁽¹⁾
CPDMA_STATERAM RX 2 Channel 2 Head Desc Pointer ⁽¹⁾
(1) Denotes CPPI 3.0 registers.
230 Peripheral Information and Timings
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