TMS320DM8127 Datasheet, PDF (42/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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4.2.1 Boot Configuration
SIGNAL
NAME
GPMC_D[15]/
BTMODE[15]
GPMC_D[14]/
BTMODE[14]
GPMC_D[13]/
BTMODE[13]
GPMC_D[12]/
BTMODE[12]
GPMC_D[11]/
BTMODE[11]
Table 4-1. Boot Configuration Terminal Functions
TYPE ⁽¹⁾
NO.
OTHER ^{(2) (3)}
Y25
I
DIS
DVDD_GPMC
V24
I
DIS
DVDD_GPMC
U23
I
DIS
DVDD_GPMC
U24
I
DIS
DVDD_GPMC
AA27
I
DIS
DVDD_GPMC
MUXED
DESCRIPTION
BOOT
GPMC
PINCNTL104
DSIS: PIN
GPMC
PINCNTL103
DSIS: PIN
GPMC
PINCNTL102
DSIS: PIN
GPMC
PINCNTL101
DSIS: PIN
GPMC
PINCNTL100
DSIS: PIN
GPMC CS0 default GPMC_Wait enable input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[15] is sampled to determine
the GPMC CS0 Wait enable:
• 0 = Wait disabled
• 1 = Wait enabled
After reset, this pin functions as GPMC multiplexed
data/address pin 15 (GPMC_D[15]).
GPMC CS0 default Address/Data multiplexing mode
input. These pins are multiplexed between ARM Cortex-
A8 boot mode and General-Purpose Memory Controller
(GPMC) peripheral functions. At reset, BTMODE[14:13]
are sampled to determine the GPMC CS0 Address/Data
multiplexing:
• 00 = Not muxed
• 01 = A/A/D muxed
• 10 = A/D muxed
• 11 = Reserved
After reset, this pin functions as GPMC multiplexed
data/address pins 14 through 13 (GPMC_D[14:13]).
GPMC CS0 default Data Bus Width input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[12] is sampled to determine
the GPMC CS0 bus width:
• 0 = 8-bit data bus
• 1 = 16-bit data bus
After reset, this pin functions as GPMC multiplexed
data/address pin 12 (GPMC_D[12]).
RSTOUT_WD_OUT Configuration. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[11] is sampled to determine
the function of the RSTOUT_WD_OUT pin:
• 0 = RSTOUT is asserted when a Watchdog Timer
reset, POR, RESET, or Emulation/Software-Global
Cold/Warm reset occurs
• 1 = RSTOUT_WD_OUT is asserted only when a
Watchdog Timer reset occurs
After reset, this pin functions as GPMC multiplexed
data/address pin 11 (GPMC_D[11]).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 5.5.1, Pullup/Pulldown Resistors and Section 8.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
42
Device Pins
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