TMS320DM8127 Datasheet, PDF (290/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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9.13.4.1.1.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 9-50. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 9-57.
A1
A1
DDR2 Device
A1
A1
Figure 9-50. DDR2 Keepout Region
NOTE
The region shown in should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the
DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided t hey are
routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the 1.8-V power plane
should cover the entire keepout region. Routes for the two DDR interfaces must be
separated by at least 4x; the more separation, the better.
9.13.4.1.1.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 9-58 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 9-58. Bulk Bypass Capacitors
No. Parameter
1 DVDD18 bulk bypass capacitor count⁽¹⁾
Min
Max Unit
6
Devices
2 DVDD18 bulk bypass total capacitance
3 DDR#1 bulk bypass capacitor count⁽¹⁾
4 DDR#1 bulk bypass total capacitance⁽¹⁾
5 DDR#2 bulk bypass capacitor count⁽²⁾
6 DDR#2 bulk bypass total capacitance⁽¹⁾⁽²⁾
60
μF
1
Devices
10
μF
1
Devices
10
μF
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].
(2) Only used on 32-bit wide DDR2 memory systems.
290 Peripheral Information and Timings
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