TMS320DM8127 Datasheet, PDF (235/365 Pages) Texas Instruments – DaVinci Video Processors

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TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
9.6.2 EMAC Electrical Data/Timing
9.6.2.1 EMAC MII and GMII Electrical Data/Timing
(see Figure 9-9)
NO.
1
t_c(MRCLK)
2
t_w(MRCLKH)
3
t_w(MRCLKL)
4
t_t(MRCLK)
Table 9-15. Timing Requirements for EMAC[x]_MRCLK - [G]MII Operation
Cycle time, EMAC[x]_MRCLK
Pulse duration,
EMAC[x]_MRCLK high
Pulse duration,
EMAC[x]_MRCLK low
Transition time,
EMAC[x]_MRCLK
1000 Mbps (1 Gbps)
(GMII Only)
MIN
MAX
8
2.8
2.8
1
OPP100/120/166
100 Mbps
MIN
MAX
40
14
14
3
10 Mbps
MIN
MAX
400
140
140
3
UNIT
ns
ns
ns
ns
1
2
4
3
EMAC[x]_MRCLK
4
Figure 9-9. EMAC[x]_MRCLK Timing (EMAC Receive) - [G]MII Operation
Table 9-16. Timing Requirements for EMAC[x]_MTCLK - [G]MII Operation
(see Figure 9-14)
OPP100/120/166
NO.
1000 Mbps (1 Gbps)
(GMII Only)
100 Mbps
10 Mbps
MIN
MAX
MIN
MAX
MIN
MAX
1
t_c(MTCLK)
Cycle time, EMAC[x]_MTCLK
8
2
t_w(MTCLKH)
Pulse duration,
EMAC[x]_MTCLK high
2.8
40
400
14
140
3
t_w(MTCLKL)
Pulse duration,
EMAC[x]_MTCLK low
2.8
14
140
4
t_t(MTCLK)
Transition time,
EMAC[x]_MTCLK
1
3
3
UNIT
ns
ns
ns
ns
1
2
4
3
EMAC[x]_MTCLK
4
Figure 9-10. EMAC[x]_MTCLK Timing (EMAC Transmit) - [G]MII Operation
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Peripheral Information and Timings 235