TMS320DM8127 Datasheet, PDF (50/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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Table 4-5. DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)
SIGNAL
NAME
DDR[0]_ODT[0]
DDR[0]_ODT[1]
DDR[0]_RST
DDR[0]_BA[2]
DDR[0]_BA[1]
DDR[0]_BA[0]
DDR[0]_A[14]
DDR[0]_A[13]
DDR[0]_A[12]
DDR[0]_A[11]
DDR[0]_A[10]
DDR[0]_A[9]
DDR[0]_A[8]
DDR[0]_A[7]
DDR[0]_A[6]
DDR[0]_A[5]
DDR[0]_A[4]
DDR[0]_A[3]
DDR[0]_A[2]
DDR[0]_A[1]
DDR[0]_A[0]
TYPE ⁽¹⁾
NO.
G18
O
H19
O
G19
O
A18
O
A20
O
F15
O
F16
O
F17
O
E17
O
D17
O
A19
O
C15
O
B15
O
E18
O
A15
O
B17
O
D15
O
E15
O
D18
O
F19
O
B19
O
OTHER ^{(2) (3)}
DESCRIPTION
IPD/DIS
DVDD_DDR[0]
IPD/DIS
DVDD_DDR[0]
IPD/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
IPU/DIS
DVDD_DDR[0]
DDR[0] On-Die Termination for Chip Select 0.
The internal pulldown (IPD) is enabled for this pin when the device is
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] On-Die Termination for Chip Select 1.
The internal pulldown (IPD) is enabled for this pin when the device is
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] Reset output
The internal pulldown (IPD) is enabled for this pin when the device is
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] Bank Address outputs
The internal pullup (IPU) is enabled for these pins when the device is
in reset and the IPU is disabled (DIS) when reset is released.
DDR[0] Address Bus
The internal pullup (IPU) is enabled for these pins when the device is
in reset and the IPU is disabled (DIS) when reset is released.
50
Device Pins
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