TMS320DM6435_17 Datasheet, PDF (94/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 3-21. Multiplexed Pins on DM6435 (continued)
SIGNAL
NAME
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
EM_CS5/GP[33]
EM_CS4/GP[32]
GP[31]
GP[30]
GP[29]
GP[28]
GP[27]
GP[26]/(FASTBOOT)
GP[25]/(BOOTMODE3)
GP[24]/(BOOTMODE2)
GP[23]/(BOOTMODE1)
GP[22]/(BOOTMODE0)
EM_D[7]/GP[21]
EM_D[6]/GP[20]
EM_D[5]/GP[19]
EM_D[4]/GP[18]
EM_D[3]/GP[17]
EM_D[2]/GP[16]
EM_D[1]/GP[15]
EM_D[0]/GP[14]
EM_CS3/GP[13]
EM_CS2/GP[12]
EM_A[3]/GP[11]
EM_A[4]/GP[10]/(AEAW2/PLLMS2)
EM_A[1]/(ALE)/GP[9]/
(AEAW1/PLLMS1)
EM_A[2]/(CLE)/GP[8]/
(AEAW0/PLLMS0)
EM_A[0]/GP[7]/(AEM2)
EM_BA[0]/GP[6]/(AEM1)
EM_BA[1]/GP[5]/(AEM0)
EM_A[12]/GP[89]
EM_A[11]/GP[90]
EM_A[10]/GP[91]
EM_A[9]/GP[92]
EM_A[8]/GP[93]
EM_A[7]/GP[94]
EM_A[6]/GP[95]
EM_A[5]/GP[96]
VLYNQ_CLOCK/GP[57]
HD0/VLYNQ_SCRUN/GP[58]
HD1/VLYNQ_RXD0/GP[59]
ZWT
NO.
D13
D12
F19
E19
D19
G19
H15
H16
H17
G17
G16
G15
F15
F18
F17
F16
E17
E18
E16
D17
D18
D16
C18
C19
B18
A17
A16
B16
B17
C17
C16
D10
C10
A9
D9
B9
C9
D8
B8
A7
C8
D7
ZDU
NO.
C17
C16
J22
H22
G22
K22
K21
J21
L19
K19
H21
L20
K20
J20
H20
F21
F22
G21
F20
E22
G20
E21
D22
C22
D21
B21
B20
A20
C21
E20
C20
B12
C12
B11
C11
A11
C10
B10
A10
A8
B9
C9
PINMUX DESCRIPTION
PINMUX GROUP
CONTROLLED BY PINMUX BIT FIELDS
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 0
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
AEM, CWENSEL
AEM, CFLDSEL
CS5SEL
CS4SEL
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
– ⁽¹⁾
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
CS3SEL
AEM
AEM
AEM
EMIFA/VPSS Sub-Block 1 AEM
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 1
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
EMIFA/VPSS Sub-Block 3
Host Block
Host Block
Host Block
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
AEM
HOSTBK
HOSTBK
HOSTBK
(1) GP[31:22] are standalone pins. They are not muxed with any other functions, but they are included in this table because they are
grouped in the EMIFA/VPSS Sub-Block 1.
94
Device Configuration
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