TMS320DM6435_17 Datasheet, PDF (186/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode⁽¹⁾ (see Figure 6-22)
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN
MAX
UNIT
18
t_d(PCLK-HDV)
Delay time, PCLK edge to HD valid
20
t_d(PCLK-VDV)
Delay time, PCLK edge to VD valid
22 t_{d(PCLK-C_FIELDV)} Delay time, PCLK edge to C_FIELD valid
2
9.5 ns
2
9.5 ns
2
9.5 ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
18
HD
20
VD
22
C_FIELD
Figure 6-22. VPFE (CCD) Master Mode Control Output Data Timing
186 Peripheral Information and Electrical Specifications
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