TMS320DM6435_17 Datasheet, PDF (139/252 Pages) Texas Instruments – Digital Media Processor

www.ti.com
TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
6.4.2 EDMA Peripheral Register Description(s)
Table 6-7 lists the EDMA registers, their corresponding acronyms, and DM6435 device memory locations.
HEX ADDRESS
0x01C0 0000 - 0x01C0 0003
0x01C0 0004
0x01C0 0008 - 0x01C0 01FF
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0250
0x01C0 0254
0x01C0 0258
0x01C0 025C
0x01C0 0260
0x01C0 0264 - 0x01C0 0283
0x01C0 0284
0x01C0 0288 - 0x01C0 02FF
0x01C0 0300
0x01C0 0304
0x01C0 0308
0x01C0 030C
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0344
0x01C0 0348
0x01C0 034C
0x01C0 0350
0x01C0 0354
0x01C0 0358
0x01C0 035C
0x01C0 0360 - 0x01C0 037C
0x01C0 0380
Table 6-7. DM6435 EDMA Registers
ACRONYM
REGISTER NAME
Channel Controller Registers
Reserved
CCCFG
EDMA3CC Configuration Register
Reserved
Global Registers
QCHMAP0
QDMA Channel 0 Mapping to PaRAM Register
QCHMAP1
QDMA Channel 1 Mapping to PaRAM Register
QCHMAP2
QDMA Channel 2 Mapping to PaRAM Register
QCHMAP3
QDMA Channel 3 Mapping to PaRAM Register
QCHMAP4
QDMA Channel 4 Mapping to PaRAM Register
QCHMAP5
QDMA Channel 5 Mapping to PaRAM Register
QCHMAP6
QDMA Channel 6 Mapping to PaRAM Register
QCHMAP7
QDMA Channel 7 Mapping to PaRAM Register
DMAQNUM0
DMA Queue Number Register 0 (Channels 00 to 07)
DMAQNUM1
DMA Queue Number Register 1 (Channels 08 to 15)
DMAQNUM2
DMA Queue Number Register 2 (Channels 16 to 23)
DMAQNUM3
DMA Queue Number Register 3 (Channels 24 to 31)
DMAQNUM4
DMA Queue Number Register 4 (Channels 32 to 39)
DMAQNUM5
DMA Queue Number Register 5 (Channels 40 to 47)
DMAQNUM6
DMA Queue Number Register 6 (Channels 48 to 55)
DMAQNUM7
DMA Queue Number Register 7 (Channels 56 to 63)
QDMAQNUM
CC QDMA Queue Number
–
Reserved
QUEPRI
Queue Priority Register
–
Reserved
EMR
Event Missed Register
EMRH
Event Missed Register High
EMCR
Event Missed Clear Register
EMCRH
Event Missed Clear Register High
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
CCERR
EDMA3CC Error Register
CCERRCLR
EDMA3CC Error Clear Register
EEVAL
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DRAEH0
DMA Region Access Enable Register High for Region 0
DRAE1
DMA Region Access Enable Register for Region 1
DRAEH1
DMA Region Access Enable Register High for Region 1
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
QRAE0
QDMA Region Access Enable Register for Region 0
Submit Documentation Feedback
Peripheral Information and Electrical Specifications 139