TMS320DM6435_17 Datasheet, PDF (4/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the DM6435 device.
Input
Clock(s)
JTAG Interface
System Control
OSC
PLLs/Clock Generator
Power/Sleep Controller
Pin Multiplexing
DSP Subsystem
C64x+t DSP CPU
128 KB L2 RAM
32 KB
L1 Pgm
80 KB
L1 Data
Boot ROM
BT.656,
Y/C,
Raw (Bayer)
16b
Video Processing Subsystem (VPSS)
Front End
CCD
Resizer
Controller Histogram/
Video
3A
Interface Preview
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Switched Central Resource (SCR)
Peripherals
Serial Interfaces
McASP McBSP
I²C
HECC
UART
System
General-
Purpose
Timer
Watchdog
Timer
PWM
GPIO
EDMA
Connectivity
EMAC
VLYNQ
With
HPI
MDIO
Program/Data Storage
DDR2 Async EMIF/
Mem Ctlr
NAND/
(32b)
(8b)
Figure 1-1. TMS320DM6435 Functional Block Diagram
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TMS320DM6435 Digital Media Processor
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