TMS320DM6435_17 Datasheet, PDF (107/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
3.7.3.11 EMIFA/VPSS Block Muxing
This block of 61 pins consists of VPSS, EMIFA, and GPIO muxed pins. The following register fields affect
the pin functions in the EMIFA/VPSS Block:
• All PINMUX0 register fields: AEM, CS5SEL, CS4SEL, CS3SEL, AEAW, CCDCSEL, HVDSEL,
CWENSEL, CFLDSEL, CI76SEL, CI54SEL, CI32SEL, and CI10SEL
The EMIFA/VPSS Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to
accommodate a wide variety of applications:
• Sub-Block 0: multiplexed between VPFE, EMIFA address/control pins, and GPIO.
• Sub-Block 1: multiplexed between EMIFA data/address/control pins, and GPIO.
• Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.
• Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6] and GPIO.
The EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register determine the power state
of the EMIFA/VPSS Block pins. The EMIFA/VPSS Block pins default to powered up. For more details on
the EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register, see Section 3.2, Power
Considerations.
To understand pin multiplexing in the EMIFA/VPSS Block, the user should start with Section 3.7.3.11.1,
EMIFA/VPSS Block Pin Selection Procedure, which outlines the procedures to select pin functions of this
block. Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, provides a pin-by-pin
multiplexing summary for the EMIFA/VPSS Block. For more information on the PINMUX0 and PINMUX1
registers, see Section 3.7.2, Pin Muxing Selection After Device Reset.
3.7.3.11.1 EMIFA/VPSS Block Pin Selection Procedure
Follow the steps below to perform pin selection for the EMIFA/VPSS Block and its sub-blocks.
1. Major Configuration Options: start with Table 3-39, EMIFA/VPSS Block Major Configuration Choices.
Based on the peripheral needs, the user should select from the major configuration options in this
block: Major Config Options A, B, and E.
2. Sub-Block 2 and Sub-Block 3 Selection: After selecting the major configuration option from
Table 3-39, EMIFA/VPSS Block Major Configuration Choices, the pin selection for Sub-Block 2 and
Sub-Block 3 is complete.
3. Sub-Block 0 Selection: Use Table 3-40 through Table 3-42, EMIFA/VPSS Sub-Block 0 Configuration
Choices, to refine Sub-Block 0 pin selections.
a. Go to the table with the Major Configuration Option chosen in Step 1.
b. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
c. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by
selecting the settings of PINMUX0 fields CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL,
CI32SEL, CI54SEL, and CI76SEL.
d. The Selection Fields columns show the settings needed to program the PINMUX0 register.
4. Sub-Block 1 Selection: Use Table 3-43 through Table 3-45, EMIFA/VPSS Sub-Block 1 Configuration
Choices, to refine Sub-Block 1 pin selection.
a. Go to the table with the Major Configuration Option chosen in Step 1.
b. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
c. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by
selecting the settings of PINMUX0 fields CS3SEL, CS4SEL, and CS5SEL.
d. The Selection Fields columns show the settings needed to program the PINMUX0 register.
After following the procedure in this section to determine pin functions for the EMIFA/VPSS Block, the
user should refer to Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, for
pin-multiplexing information on a pin-by-pin basis.
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