TMS320DM6435_17 Datasheet, PDF (162/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
For details on the PLL initialization software sequence, see theTMS320DM643x DMP DSP Subsystem
Reference Guide (literature number SPRU978).
For more information on the clock domains and their clock ratio restrictions, see Section 6.3.4, DM6435
Power and Clock Domains.
6.7.2 PLL Controller Register Description(s)
A summary of the PLL controller registers is shown in Table 6-18. For more details, see the
TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978).
Table 6-18. PLL and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
0x01C4 0800
0x01C4 08E4
0x01C4 0900
0x01C4 0910
0x01C4 0918
0x01C4 091C
0x01C4 0920
0x01C4 0924
0x01C4 0928
0x01C4 092C
0x01C4 0938
0x01C4 093C
0x01C4 0940
0x01C4 0944
0x01C4 0948
0x01C4 094C
0x01C4 0950
0x01C4 0960
0x01C4 0964
0x01C4 0C00
0x01C4 0D00
0x01C4 0D10
0x01C4 0D18
0x01C4 0D1C
0x01C4 0D20 - 0x01C4 0D2C
0x01C4 0D2C
0x01C4 0D38
0x01C4 0D3C
0x01C4 0D40
0x01C4 0D44
0x01C4 0D48
0x01C4 0D4C
0x01C4 0D50
REGISTER ACRONYM
DESCRIPTION
Controller Registers
PID
Peripheral ID Register
RSTYPE
Reset Type Register
PLLCTL
PLL Controller 1 PLL Control Register
PLLM
PLL Controller 1 PLL Multiplier Control Register
PLLDIV1
PLL Controller 1 Divider 1 Register (SYSCLK1)
PLLDIV2
PLL Controller 1 Divider 2 Register (SYSCLK2)
PLLDIV3
PLL Controller 1 Divider 3 Register (SYSCLK3)
OSCDIV1
PLL Controller 1 Oscillator Divider 1 Register (OBSCLK) [CLKOUT0 pin]
–
Reserved
–
Reserved
PLLCMD
PLL Controller 1 Command Register
PLLSTAT
PLL Controller 1 Status Register (Shows PLLC1 Status)
ALNCTL
PLL Controller 1 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
DCHANGE
PLL Controller 1 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
CKEN
PLL Controller 1 Clock Enable Control Register
CKSTAT
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
SYSTAT
PLL Controller 1 SYSCLK Status Register (Indicates SYSCLK on/off Status)
–
Reserved
–
Reserved
PLL2 Controller Registers
PID
Peripheral ID Register
PLLCTL
PLL Controller 2 PLL Control Register
PLLM
PLL Controller 2 PLL Multiplier Control Register
PLLDIV1
PLL Controller 2 Divider 1 Register (SYSCLK1)
–
Reserved
–
Reserved
BPDIV
PLL Controller 2 Bypass Divider Register (SYSCLKBP)
PLLCMD
PLL Controller 2 Command Register
PLLSTAT
PLL Controller 2 Status Register (Shows PLLC2 Status)
ALNCTL
PLL Controller 2 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
DCHANGE
PLL Controller 2 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has Been Modified)
–
Reserved
CKSTAT
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
SYSTAT
PLL Controller 2 SYSCLK Status Register (Indicates SYSCLK on/off Status)
162 Peripheral Information and Electrical Specifications
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