TMS320DM6435_17 Datasheet, PDF (29/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode 1, AEM[2:0] = 001)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEAW[2:0], AEM[2:0], etc.). For more details,
see Section 3.7, Multiplexed Pin Configurations.
This pin is multiplexed between EMIFA and GPIO.
EM_CS2/
GP[12]
C19 C22 I/O/Z
IPD
DV_DD33
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
asynchronous memories (i.e., NOR flash).
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper
device operation, an external pullup resistor must be used to ensure
the EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA and GPIO.
EM_CS3/
GP[13]
C18 D22 I/O/Z
IPD
DV_DD33
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper
device operation, an external pullup resistor must be used to ensure
the EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA and GPIO.
EM_CS4/
GP[32]
E19 H22 I/O/Z
IPD
DV_DD33
For EMIFA, it is Chip Select 4 output EM_CS4 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper
device operation, an external pullup resistor must be used to ensure
the EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA and GPIO.
EM_CS5/
GP[33]
F19 J22 I/O/Z
C_WE/EM_R/W/
GP[35]
EM_WAIT/
(RDY/BSY)
EM_OE
EM_WE
D13 C17 I/O/Z
E15 D20
D15 D19
E14 C19
I/O/Z
I/O/Z
I/O/Z
EM_BA[0]/GP[6]/
(AEM1)
C17 E20 I/O/Z
EM_BA[1]/GP[5]/
(AEM0)
C16 C20 I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
For EMIFA, it is Chip Select 5 output EM_CS5 for use with
asynchronous memories (i.e., NOR flash).
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper
device operation, an external pullup resistor must be used to ensure
the EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
For EMIFA, it is read/write output EM_R/W.
For EMIFA (ASYNC/NOR), this pin is wait state extension input
EM_WAIT.
For EMIFA, it is output enable output EM_OE.
For EMIFA, it is write enable output EM_WE.
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this is the Bank Address 0 output (EM_BA[0]). When
connected to an 8-bit asynchronous memory, this pin is the lowest
order bit of the byte address.
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this is the Bank Address 1 output EM_BA[1]. When
connected to an 8-bit asynchronous memory, this pin is the 2nd bit of
the address.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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