TMS320DM6435_17 Datasheet, PDF (179/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-31. Preview Engine Register Descriptions (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
0x01C7 080C
VERT_INFO
0x01C7 0810
RSDR_ADDR
0x01C7 0814
RADR_OFFSET
0x01C7 0818
DSDR_ADDR
0x01C7 081C
DRKF_OFFSET
0x01C7 0820
WSDR_ADDR
0x01C7 0824
WADD_OFFSET
0x01C7 0828
AVE
0x01C7 082C
HMED
0x01C7 0830
NF
0x01C7 0834
WB_DGAIN
0x01C7 0838
WBGAIN
0x01C7 083C
WBSEL
0x01C7 0840
CFA
0x01C7 0844
BLKADJOFF
0x01C7 0848
RGB_MAT1
0x01C7 084C
RGB_MAT2
0x01C7 0850
RGB_MAT3
0x01C7 0854
RGB_MAT4
0x01C7 0858
RGB_MAT5
0x01C7 085C
RGB_OFF1
0x01C7 0860
RGB_OFF2
0x01C7 0864
CSC0
0x01C7 0868
CSC1
0x01C7 086C
CSC2
0x01C7 0870
CSC_OFFSET
0x01C7 0874
CNT_BRT
0x01C7 0878
CSUP
0x01C7 087C
SETUP_YC
0x01C7 0880
SET_TBL_ADDRESS
0x01C7 0884
SET_TBL_DATA
DESCRIPTION
Vertical Information/Setup
Read Address From SDRAM
Line Offset for the Read Data
Dark Frame Address From SDRAM
Line Offset for the Dark Frame Data
Write Address to the SDRAM
Line Offset for the Write Data
Input Formatter/Averager
Horizontal Median Filter
Noise Filter
White Balance Digital Gain
White Balance Coefficients
White Balance Coefficients Selection
CFA Register
Black Adjustment Offset
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Coefficients
RGB2RGB Blending Matrix Offsets
RGB2RGB Blending Matrix Offsets
Color Space Conversion Coefficients
Color Space Conversion Coefficients
Color Space Conversion Coefficients
Color Space Conversion Offsets
Contrast and Brightness Settings
Chrominance Suppression Settings
Maximum/Minimum Y and C Settings
Setup Table Addresses
Setup Table Data
6.10.1.3 Resizer
The resizer module can accept input image/video data from either the preview engine or DDR2. The
output of the resizer module is sent to DDR2. The following features are supported by the resizer module.
• An output width up to 1280 horizontal pixels.
• Input from external DDR2.
• Up to 4x upsampling (digital zoom).
• Bi-cubic interpolation (4-tap horizontal, 4-tap vertical) can be implemented with the programmable filter
coefficients.
• 8 phases of filter coefficients.
• Optional bi-linear interpolation for the chrominance components.
• Up to 1/4x downsampling
• 4-tap horizontal and 4-tap vertical filter coefficients (with 8-phases) for 1x to 1/2x downsampling
• 1/2x to 1/4x downsampling, for 7-tap mode with 4-phases.
• Resizing either YUV 4:2:2 packed data (16-bits) or color separate data (8-bit data within DDR) that is
contiguous.
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Peripheral Information and Electrical Specifications 179