LM3S1636_13 Datasheet, PDF (93/655 Pages) Texas Instruments – Stellaris Microcontroller

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Stellaris^® LM3S1636 Microcontroller
3.1.3
3.1.4
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 69 for more information).
Table 3-2 on page 93 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris Microcontroller” on page 97 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type
Strongly Ordered
Device
Normal
Description
All accesses to Strongly Ordered memory occur in program order.
Memory-mapped peripherals
Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
July 24, 2012
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