LM3S1636_13 Datasheet, PDF (372/655 Pages) Texas Instruments – Stellaris Microcontroller

Watchdog Timer
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Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STALL
reserved
Type RO
RO
RO
RO
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:9
8
7:0
Name
reserved
STALL
reserved
Type
RO
R/W
RO
Reset
0x00
0
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped with a debugger,
the watchdog timer stops counting. Once the microcontroller is restarted,
the watchdog timer resumes counting.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
372
July 24, 2012
Texas Instruments-Production Data