LM3S1636_13 Datasheet, PDF (155/655 Pages) Texas Instruments – Stellaris Microcontroller

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Stellaris^® LM3S1636 Microcontroller
4.1
Block Diagram
Figure 4-1. JTAG Module Block Diagram
TRST
TCK
TMS
TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
4.2 Signal Description
Table 4-1 on page 155 list the external signals of the JTAG/SWD controller and describe the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see “Commit
Control” on page 287. The column in the table below titled "Pin Assignment" lists the GPIO pin
placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 301) is set to choose the JTAG/SWD function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 280.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
TRST
89
I
TTL
JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
July 24, 2012
155
Texas Instruments-Production Data