LM3S1636_13 Datasheet, PDF (594/655 Pages) Texas Instruments – Stellaris Microcontroller

Signal Tables
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Table 18-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
38
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
39
GND
-
Power Ground reference for logic and I/O pins.
40
PG5
I/O
TTL
GPIO port G bit 5.
41
PG4
I/O
TTL
GPIO port G bit 4.
42
PF7
I/O
TTL
GPIO port F bit 7.
43
PF6
I/O
TTL
GPIO port F bit 6.
44
VDD
-
Power Positive supply for I/O and some logic.
45
GND
-
Power Ground reference for logic and I/O pins.
PF5
I/O
TTL
GPIO port F bit 5.
46
C1o
O
TTL
Analog comparator 1 output.
47
PF0
I/O
TTL
GPIO port F bit 0.
48
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
51
HIB
O
OD
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
XOSC0
52
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
53
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
54
GND
-
Power Ground reference for logic and I/O pins.
VBAT
55
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56
VDD
-
Power Positive supply for I/O and some logic.
57
GND
-
Power Ground reference for logic and I/O pins.
PF4
I/O
TTL
GPIO port F bit 4.
58
C0o
O
TTL
Analog comparator 0 output.
PF3
I/O
TTL
GPIO port F bit 3.
59
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PF2
I/O
TTL
GPIO port F bit 2.
60
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
61
PF1
I/O
TTL
GPIO port F bit 1.
62
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
63
GND
-
Power Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
65
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
I/O
TTL
GPIO port B bit 0.
66
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
594
July 24, 2012
Texas Instruments-Production Data