CC430F6137_14 Datasheet, PDF (91/120 Pages) Texas Instruments – MSP430™ SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
to LCD_B
(n/a CC430F513x)
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
from Port Mapping
P1OUT.x
from Port Mapping
P1SEL.x
P1IN.x
to Port Mapping
P1IRQ.x
0
Direction
1
0: Input
1: Output
0
1
EN
D
P1IE.x
P1IFG.x
EN
Q
Set
Pad Logic
DVSS 0
DVCC 1
1
P1DS.x
0: Low drive
1: High drive
Bus
Keeper
P1.5/P1MAP5(/R23)
P1.6/P1MAP6(/R13)
P1.7/P1MAP7(/R03)
P1SEL.x
P1IES.x
Interrupt
Edge
Select
CC430F513x devices don't provide LCD functionality on port P1 pins.
PIN NAME (P1.x)
P1.5/P1MAP5/R23
P1.6/P1MAP6/R13/
LCDREF
P1.7/P1MAP7/R03
Table 50. Port P1 (P1.5 to P1.7) Pin Functions
x
FUNCTION
CONTROL BITS/SIGNALS⁽¹⁾
P1DIR.x
P1SEL.x
P1MAPx
5 P1.5 (I/O)
Mapped secondary digital function - see Table 9
R23⁽³⁾ (not available on CC430F513x)
I: 0; O: 1
0
0; 1 ⁽²⁾
1
X
1
X
≤ 30⁽²⁾
= 31
6 P1.6 (I/O)
Mapped secondary digital function - see Table 9
R13/LCDREF⁽³⁾ (not available on CC430F513x)
I: 0; O: 1
0
0; 1⁽²⁾
1
X
1
X
≤ 30⁽²⁾
= 31
7 P1.7 (I/O)
Mapped secondary digital function - see Table 9
R03⁽³⁾ (not available on CC430F513x)
I: 0; O: 1
0
0; 1⁽²⁾
1
X
1
X
≤ 30⁽²⁾
= 31
(1) X = don't care
(2) According to mapped function - see Table 9.
(3) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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