CC430F6137_14 Datasheet, PDF (22/120 Pages) Texas Instruments – MSP430™ SoC With RF Core

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
www.ti.com
Table 9. Port Mapping, Mnemonics and Functions (continued)
VALUE
27
28
29
30
31 (0FFh)⁽⁶⁾
PxMAPy MNEMONIC
Reserved
Reserved
Reserved
Reserved
PM_ANALOG
INPUT PIN FUNCTION (PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
None
DVSS
None
DVSS
None
DVSS
None
DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent
parasitic cross currents when applying analog signals.
(6) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
PIN
P1.0/P1MAP0
P1.1/P1MAP1
P1.2/P1MAP2
P1.3/P1MAP3
P1.4/P1MAP4
P1.5/P1MAP5
P1.6/P1MAP6
P1.7/P1MAP7
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
P3.0/P3MAP0
P3.1/P3MAP1
P3.2/P3MAP2
P3.3/P3MAP3
P3.4/P3MAP4
P3.5/P3MAP5
P3.6/P3MAP6
P3.7/P3MAP7
Table 10. Default Mapping
PxMAPy MNEMONIC
PM_RFGDO0
PM_RFGDO2
PM_UCB0SOMI/PM_UCB0SCL
PM_UCB0SIMO/PM_UCB0SDA
PM_UCB0CLK/PM_UCA0STE
PM_UCA0RXD/PM_UCA0SOMI
PM_UCA0TXD/PM_UCA0SIMO
PM_UCA0CLK/PM_UCB0STE
PM_CBOUT1/PM_TA1CLK
PM_TA1CCR0A
PM_TA1CCR1A
PM_TA1CCR2A
PM_RTCCLK
PM_SVMOUT
PM_ACLK
PM_ADC12CLK/PM_DMAE0
PM_CBOUT0/PM_TA0CLK
PM_TA0CCR0A
PM_TA0CCR1A
PM_TA0CCR2A
PM_TA0CCR3A
PM_TA0CCR4A
PM_RFGDO1
PM_SMCLK
INPUT PIN FUNCTION
(PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
None
Radio GDO0
None
Radio GDO2
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_A0 UART RXD (Direction controlled by USCI - input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI),
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
TA1 clock input
Comparator_B output
TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
None
RTCCLK output
None
SVM output
None
ACLK output
DMA external trigger input
ADC12CLK output
TA0 clock input
Comparator_B output
TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
None
Radio GDO1
None
SMCLK output
22
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