CC430F6137_14 Datasheet, PDF (21/120 Pages) Texas Instruments – MSP430™ SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
Port Mapping Controller
The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of
ports P1 through P3.
VALUE
0
1 ⁽¹⁾
2 ⁽¹⁾
3
4
5
6
7 ⁽¹⁾
8
9
10
11
12
13
14
15
16
17 ⁽²⁾
18 ⁽²⁾
19 ⁽³⁾
20 ⁽⁴⁾
21 ⁽⁴⁾
22 ⁽⁵⁾
23
24
25
26
Table 9. Port Mapping, Mnemonics and Functions
PxMAPy MNEMONIC
PM_NONE
PM_CBOUT0
PM_TA0CLK
PM_CBOUT1
PM_TA1CLK
PM_ACLK
PM_MCLK
PM_SMCLK
PM_RTCCLK
PM_ADC12CLK
PM_DMAE0
PM_SVMOUT
PM_TA0CCR0A
PM_TA0CCR1A
PM_TA0CCR2A
PM_TA0CCR3A
PM_TA0CCR4A
PM_TA1CCR0A
PM_TA1CCR1A
PM_TA1CCR2A
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_RFGDO0
PM_RFGDO1
PM_RFGDO2
Reserved
INPUT PIN FUNCTION (PxDIR.y = 0)
OUTPUT PIN FUNCTION
(PxDIR.y = 1)
None
DVSS
Comparator_B output (on TA0 clock
input)
TA0 clock input
-
-
Comparator_B output (on TA1 clock
input)
TA1 clock input
-
None
ACLK output
None
MCLK output
None
SMCLK output
None
RTCCLK output
-
ADC12CLK output
DMA external trigger input
-
None
SVM output
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
USCI_A0 UART RXD (Direction controlled by USCI - input)
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
Radio GDO0 (direction controlled by Radio)
Radio GDO1 (direction controlled by Radio)
Radio GDO2 (direction controlled by Radio)
None
DVSS
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin
drives only the logical 0 to V_SS level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will
be forced to 3-wire SPI mode even if 4-wire mode is selected.
Copyright © 2009–2013, Texas Instruments Incorporated
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CC430F5135 CC430F5133