CC430F6137_14 Datasheet, PDF (101/120 Pages) Texas Instruments – MSP430™ SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
Port P5, P5.1, Input/Output With Schmitt Trigger
to XT1
Pad Logic
P5REN.1
P5DIR.1
P5OUT.1
Module X OUT
P5SEL.0
XT1BYPASS
P5IN.1
Module X IN
0
1
0
1
EN
D
DVSS 0
DVCC 1
1
P5DS.x
0: Low drive
1: High drive
Bus
Keeper
P5.1/XOUT
PIN NAME (P5.x)
P5.0/XIN
P5.1/XOUT
Table 54. Port P5 (P5.0 and P5.1) Pin Functions
x
FUNCTION
P5DIR.x
CONTROL BITS/SIGNALS⁽¹⁾
P5SEL.0
P5SEL.1
0 P5.0 (I/O)
XIN crystal mode⁽²⁾
XIN bypass mode⁽²⁾
I: 0; O: 1
0
X
X
1
X
X
1
X
1 P5.1 (I/O)
I: 0; O: 1
0
X
XOUT crystal mode⁽³⁾
X
1
X
P5.1 (I/O)⁽³⁾
X
1
X
XT1BYPASS
X
0
1
X
0
1
(1) X = don't care
(2) Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as
general-purpose I/O.
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