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CC430F6137_14 Datasheet, PDF (55/120 Pages) Texas Instruments – MSP430™ SoC With RF Core
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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
SVSLE = 0, PMMCOREV = 2
0
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
tpd(SVSL)
SVSL propagation delay
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
t(SVSL)
SVSL on or off delay time
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
12.5
100
MAX
UNIT
nA
nA
µA
µs
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
SVMLE = 0, PMMCOREV = 2
0
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
tpd(SVML) SVML propagation delay
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
t(SVML)
SVML on or off delay time
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
12.5
100
MAX
UNIT
nA
nA
µA
µs
µs
Wake Up From Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tWAKE-UP-FAST
Wake-up time from LPM2, LPM3, or
LPM4 to active mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
fMCLK ≥ 4.0 MHz
fMCLK < 4.0 MHz
tWAKE-UP-SLOW
Wake-up time from LPM2, LPM3 or
LPM4 to active mode(2)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-RESET
Wake-up time from RST or BOR
event to active mode(3)
TYP MAX UNIT
5
µs
6
150 165 µs
2
3 ms
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low side monitor (SVML). Fastest wake-up times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family
User's Guide (SLAU259).
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the CC430 Family User's Guide (SLAU259).
(3) This value represents the time from the wake-up event to the reset vector execution.
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